This invention relates to the realization of planar layers in semiconductor wafer fabrication; and more particularly to a process for implementing chemical-mechanical planarization (xe2x80x9cCMPxe2x80x9d) in the manufacture of Damascene structures to achieve both global and local planarization without generating excessive unwanted topography.
Integrated circuits are comprised of arrays of interconnected devices and components such as transistors, resistors, diodes and capacitors formed as patterns on a series of vertically stacked films on a substrate. In fabricating integrated circuits, it is critical that the film layers on each substrate have xe2x80x9ctopographical planarityxe2x80x9d: that is, the surface features of a given film layer must fall in a common plane, and the stacked planes must be parallel. A lack of planarity causes problems in photolithography and etch steps as well as other problems. The requirement of maintaining planarity becomes increasingly critical with each additional conductive or dielectric layer. At several points in the fabrication process, therefore, the wafer is xe2x80x9cplanarizedxe2x80x9d to minimize any topography.
As used herein, the term xe2x80x9ctopographyxe2x80x9d refers to anomolies in the surfaces of material layers within the wafer, which give rise to lack of surface planarity. Certain topographic conditions are xe2x80x9cglobalxe2x80x9d, in that the anomaly exists across most or all of the surface layer. Other topographic conditions are xe2x80x9clocalxe2x80x9d in that the anomalies show up in one or many discrete areas along the layer.
In the CMP process, a wafer of semiconductor material is held on a rotating polishing platen while a slurry-wetted polishing pad is rotated against the material surface. The slurry is a mixture of either a basic or an acidic solution to which is added abrading material such as alumina or silica particles. The liquid portion of the slurry chemically reacts with the surface of the semiconductor material to remove, loosen or modify the surface material. Concurrently, as the polishing platen and pad rotate, the particles suspended in the slurry mechanically remove surface material. Planarization processes can be applied to conductive, semiconductive or dielectric insulating layers.
For several reasons, there is increasing reliance on CMP technology. For example, an important application of CMP technology is to the Damascene process, which produces conductive interconnects and other details that are directly defined without using a reactive ion etch process. The Damascene process has the potential to fabricate submicron geometry interconnects. Further, copper is emerging as the preferred metal for back end-of-line metallization for integrated circuits. CMP is the most feasible method by which the copper can be patterned to the required xe2x80x9cglobal planarityxe2x80x9d for these wafers.
Achieving topological planarity when using the CMP process depends in large part on process xe2x80x9cselectivityxe2x80x9d, or how well the polishing performance can be engineered to remove high areas on the substrate at a greater rate than it removes low areas. The metrics governing the polish performance of a metal CMP process are designed to minimize the topographic conditions of dishing, erosion and line thinning of the defined structures. Dishing is more relevant at higher metal layers where wider metal lines typically occur. Erosion appears to be the primary factor in polishing performance at lower levels of metallization where higher pattern density structures are defined. These topographic conditions are further described hereinafter.
In current CMP treatment of copper layers, typically a single-slurry, single-step polish process is employed. An oxide buff polish may be included as a second step. The slurry is formulated with a low copper:barrier selectivity approaching 1:1; and as high a copper:dielectric selectivity as possible. The process does not, however, satisfactorily reduce the generation of topography. The consequences include overall line thinning which adversely affects circuit performance through resistance increases of the conducting line, which in turn causes increased RC delay. Topography also can cause metal stringers at subsequent levels, cause depth-of-focus violations during subsequent lithography, cause etch margin errors due to dielectric thickness variations for spun-on dielectrics, and necessitate increased overpolish requirements. All of these problems drive up the cost of fabrication and decrease the line yields.
The invention is a metal CMP process which minimizes topography by partitioning of the copper polish step into a 2-stage process for separate bulk metal removal and interface clearing. First, in stage 1 the initial metallic topography is planarized both globally and locally by CMP removal of a preponderance of overlying metal without penetrating to dielectric or barrier materials. The focus is to complete stage 1 with a minimum of CMP-generated global topography, thus to produce a metal surface as flat as possible. There is no issue in stage 1 of controlling the barrier:dielectric removal rate, since stage 1 ends prior to exposing the barrier. Then in stage 2, using a slurry having a 1:1:1 removal rate selectivity as to the metal/barrier/dielectric materials, further removal proceeds with attention to good polishing uniformity, the object being to preserve the optimally flat topography achieved in stage 1. Polishing proceeds in stage 2 until a selected plane containing all three materials is reached, for which in accordance with the invention the high degree of stage 1 planarity has been maintained.
In a further embodiment, stage I may be segmented into a first phase in which a high rate of CMP is maintained, and a second phase where the CMP rate is reduced to allow a more controlled removal of material.